Bipolar transistor and method for fabricating the same

ABSTRACT

An n-type first single crystal silicon layer is provided as collector region over a silicon substrate with a first insulating film interposed therebetween. A p-type first polysilicon layer is provided as an extension of a base region over the first single crystal silicon layer with a second insulating film interposed therebetween. A p-type second single crystal silicon layer is provided as intrinsic base region on a side of the first single crystal silicon layer, second insulating film and first polysilicon layer. An n-type third single crystal silicon layer is provided as emitter region on a side of the second single crystal silicon layer. And an n-type third polysilicon layer is provided on the first insulating film as extension of an emitter region and is connected to a side of the third single crystal silicon layer.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a bipolar transistor with a baseregion extending vertically to the surface of a semiconductor substrateand to a method for fabricating such a transistor.

[0002] A bipolar transistor operating at even higher speeds is in highdemand to further improve the performance of a semiconductor integratedcircuit device.

[0003] Reduction in base-emitter or base-collector parasitic capacitanceplays a key role in increasing the operating speed of a bipolartransistor. To minimize the parasitic capacitance, a junction regionbetween the base and emitter regions or between the base and collectorregions should preferably have its area reduced.

[0004] For that purpose, the base-emitter or base-collector junctionregion is formed by lithography according to a known technique to makeits area as small as possible.

[0005] When the lithography technique is adopted, however, the precisionof fine-line processing is dependent on the wavelength of radiationemitted from a light source for the lithographic process. In otherwords, it is difficult to define a fine-line pattern at a precisionequal to or smaller than the wavelength of the radiation. Thus, the areaof the junction region cannot be reduced below a certain limit.

[0006] Japanese Laid-Open Publication No. 5-182978 discloses analternative method for reducing the base-emitter or base-collectorjunction area.

[0007] Hereinafter, the method for fabricating a bipolar transistor asdisclosed in the publication identified above will be described withreference to FIGS. 3(a) through 3(d).

[0008] First, as shown in FIG. 3(a), a silicon-on-insulator (SOI)substrate is prepared. In the SOI substrate, an n-type first singlecrystal silicon layer 102 is formed over a silicon substrate 100 with afirst silicon dioxide film 101 interposed therebetween. Next, the firstsingle crystal silicon layer 102 is selectively doped with As ions,thereby defining a collector connection region 103. In this case, thefirst single crystal silicon layer 102 will be a collector region. Then,a second silicon dioxide film 104 is deposited by a CVD process on thefirst single crystal silicon layer 102 and collector connection region103, and a p-type first polysilicon layer 105 is deposited by a CVDprocess on the second silicon dioxide film 104.

[0009] Next, as shown in FIG. 3(b), an opening 106 is provided throughthe first polysilicon layer 105, second silicon dioxide film 104 andfirst single crystal silicon layer 102. The opening 106 is provided toform a transistor thereon. Subsequently, an epitaxy process is performedunder the conditions so defined as to grow epitaxial and polysiliconlayers at the same time. As a result of this process, a p-type secondsingle crystal silicon layer 107 is formed on the side faces of thefirst single crystal silicon layer 102. Also, a p-type secondpolysilicon layer 108 is deposited to cover the upper and side faces ofthe first polysilicon layer 105, the side faces of the second silicondioxide film 104 and the upper surface of the first silicon dioxide film101. Then, the layers 107 and 108 are etched anisotropically, therebyleaving the p-type second single crystal silicon layer 107 on the sidefaces of the first single crystal silicon layer 102 and the secondpolysilicon layer 108 on the side faces of the first polysilicon layer105 and second silicon dioxide film 104, respectively. The second singlecrystal silicon layer 107 will be an intrinsic base region, while thefirst and second polysilicon layers 105 and 108 will together constitutea base connection region.

[0010] Then, a resist pattern is defined over the entire surface of thefirst polysilicon layer 105 and then etched under controlled conditions,thereby partially leaving the resist pattern 109 inside the opening 106where an emitter region will be defined as shown in FIG. 3(c).Subsequently, a third silicon dioxide film 110 is deposited on parts ofthe first and second polysilicon layers 105 and 108 that are not coveredwith the resist pattern 109.

[0011] Thereafter, as shown in FIG. 3(d), the resist pattern 109 isstripped. Then, an n-type third single crystal silicon layer 111 isformed on the side faces of the second single crystal silicon layer 107(i.e., the exposed inner wall of the opening 106 that is not coveredwith the third silicon dioxide film 110). The third single crystalsilicon layer 111 will be an emitter region. Subsequently, an n-typethird polysilicon layer 112 is deposited over the entire surface of thethird silicon dioxide film 110 as well as over the inner wall of theopening 106, and then patterned. The patterned third polysilicon layer112 will be an emitter connection region.

[0012] Next, the third silicon dioxide film 110 and the firstpolysilicon layer 105 are patterned, and then the second silicon dioxidefilm 104 is patterned. Thereafter, openings are provided in the thirdsilicon dioxide film 110 to form electrodes thereon. Subsequently, analuminum film is deposited over the collector connection region 103,second and third silicon dioxide films 104, 110 and third polysiliconlayer 112 and then patterned. As a result, emitter, base and collectorelectrodes 114A, 114B and 114C are formed to be connected to the thirdpolysilicon layer 112, first polysilicon layer 105 and collectorconnection regions 103, respectively. In this manner, the prior artbipolar transistor is completed.

[0013] In the prior art bipolar transistor, the area of the junctionbetween the first and second single crystal silicon layers 102 and 107functioning as the collector and intrinsic base regions is defined bythe thickness of the first single crystal silicon layer 102. Thus, thebase-collector parasitic capacitance can be reduced if the first singlecrystal silicon layer 102 is thinned. Also, the area of the junctionbetween the second and third single crystal silicon layers 107 and 111,which function as the intrinsic base and emitter regions, respectively,is defined by the height of the third single crystal silicon layer 111,or the thickness of the resist pattern 109 left inside the opening 106.Thus, the base-emitter parasitic capacitance can be reduced if theresist pattern 109 left within the opening 106 is thinned.

[0014] In the prior art bipolar transistor, however, it is difficult toprecisely control the thickness of the resist pattern 109 left withinthe opening 106. This is because the resist pattern 109 is defined byetching the resist pattern that has been deposited over the entiresurface of the first polysilicon layer 105 under controlled conditions.

[0015] For that reason, it is also difficult to precisely control theheight of the third single crystal silicon layer 111, or the area of thebase-emitter junction region. As a result, the base-emitter parasiticcapacitance becomes variable, thus making the electrical characteristicsof the bipolar transistor inconstant.

SUMMARY OF THE INVENTION

[0016] An object of the present invention is increasing the operatingspeed of a bipolar transistor by lowering the base-collector andbase-emitter parasitic capacitance values through the reduction in areaof base-collector and base-emitter junction regions.

[0017] Another object of the present invention is stabilizing theelectrical characteristics of the bipolar transistor by preciselycontrolling the base-emitter junction area or parasitic capacitance.

[0018] To achieve these objects, a bipolar transistor according to thepresent invention includes: a first semiconductor layer of a firstconductivity type, which is formed over a semiconductor substrate; asecond semiconductor layer of a second conductivity type, which isformed over the first semiconductor layer with an insulating filminterposed therebetween; a third semiconductor layer of the secondconductivity type, which is formed on side faces of the first and secondsemiconductor layers and the insulating film; a fourth semiconductorlayer of the first conductivity type, which is formed on a side of thethird semiconductor layer, the side being opposite to the other side ofthe third semiconductor layer that is in contact with the first andsecond semiconductor layers; and a fifth semiconductor layer of thefirst conductivity type, which is formed over the semiconductorsubstrate to be in contact with the fourth semiconductor layer. Thethird semiconductor layer is defined as a base region. The firstsemiconductor layer is defined as one of collector and emitter regions,while the fourth semiconductor layer is defined as the other of thecollector and emitter regions. The second semiconductor layer is definedas an extension of the third semiconductor layer. And the fifthsemiconductor layer is defined as an extension of the fourthsemiconductor layer.

[0019] A method for fabricating a bipolar transistor according to thepresent invention includes the steps of: forming a first semiconductorlayer of a first conductivity type, an insulating film and a secondsemiconductor layer of a second conductivity type in this order over asemiconductor substrate; forming a third semiconductor layer of thesecond conductivity type on respective side faces of the first andsecond semiconductor layers and the insulating film; forming a fourthsemiconductor layer of the first conductivity type on a side of thethird semiconductor layer, the side being opposite to the other side ofthe third semiconductor layer that is in contact with the first andsecond semiconductor layers; forming a fifth semiconductor layer of thefirst conductivity type over the semiconductor substrate such that thefifth semiconductor layer is in contact with the fourth semiconductorlayer; and defining the third semiconductor layer as a base region, thefirst semiconductor layer as one of collector and emitter regions, thefourth semiconductor layer as the other of the collector and emitterregions, the second semiconductor layer as an extension of the thirdsemiconductor layer and the fifth semiconductor layer as an extension ofthe fourth semiconductor layer, respectively.

[0020] According to the present invention, the area of a junction regionbetween the fourth semiconductor layer to be collector or emitter regionand the third semiconductor layer to 10 be base region is defined by theheight of the third semiconductor layer. Also, since the thirdsemiconductor layer is formed on the respective side faces of the firstand second semiconductor layers and the insulating film, the height ofthe third semiconductor layer is defined as a total thickness of thefirst and second semiconductor layers and the insulating film. And thethicknesses of the first and second semiconductor layers and theinsulating film are each controllable precisely. Thus, the area of thecollector-base or emitter-base junction region is controllableprecisely, so is the collector-base or emitter-base parasiticcapacitance.

[0021] As a result, the electrical characteristics of the bipolartransistor can be stabilized.

[0022] In addition, the thicknesses of the first and secondsemiconductor layers and the insulating film can all be reduced byadjusting the deposition conditions. Thus, the operating speed of thebipolar transistor can be increased by reducing the collector-base oremitter-base parasitic capacitance through the reduction in totalthickness of the first and second semiconductor layers and theinsulating film.

[0023] In one embodiment of the present invention, the area of thesecond semiconductor layer is preferably smaller than that of the firstsemiconductor layer.

[0024] In such an embodiment, an extension electrode can be formed to bein direct contact with the first semiconductor layer. That is to say,there is no need to provide any extension region for the firstsemiconductor layer separately, thus cutting down the number ofnecessary process steps.

[0025] In another embodiment, the first and fourth semiconductor layersare preferably silicon layers, while the third semiconductor layer ispreferably a silicon germanium layer.

[0026] The band gap of a silicon germanium layer is smaller than that ofa silicon layer. Thus, discontinuity is caused between the valence bandof the first and fourth semiconductor layers and that of the thirdsemiconductor layer in such an embodiment. As a result, the number ofholes injected from the base region into the emitter region decreasesand therefore, the frequency characteristics of the bipolar transistorimprove.

[0027] In still another embodiment, the fourth and fifth semiconductorlayers are preferably formed in a single process step. In such anembodiment, increase in number of process steps can be minimized bydoing so.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1 is a cross-sectional view of a bipolar transistor accordingto an exemplary embodiment of the present invention.

[0029] FIGS. 2(a) through 2(d) are cross-sectional views illustratingrespective process steps for fabricating the bipolar transistoraccording to the present invention.

[0030] FIGS. 3(a) through 3(d) are cross-sectional views illustratingrespective process steps for fabricating a prior art bipolar transistor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Hereinafter, a bipolar transistor according to an exemplaryembodiment of the present invention will be described with reference toFIG. 1.

[0032] As shown in FIG. 1, an n-type first single crystal silicon layer(i.e., first semiconductor layer) 10c doped with arsenic (As) isprovided over a silicon substrate 10a with a first insulating film 10bof silicon dioxide interposed therebetween. The silicon substrate 10a,first insulating film 10b and first single crystal silicon layer 10ctogether constitute an SOI substrate 10. The first single crystalsilicon layer 10c is defined as collector region.

[0033] A p-type first polysilicon layer (i.e., second semiconductorlayer) 12 doped with boron (B) is provided over the first single crystalsilicon layer 10c with a second insulating film 11 of silicon dioxideinterposed therebetween. The thickness of the second insulating film 11may be 100 nm. The first polysilicon layer 12 is defined as an extensionof an intrinsic base region as will be described later.

[0034] A p-type second single crystal silicon layer (i.e., thirdsemiconductor layer) 14 with a thickness of 60 nm is provided on oneside of the first single crystal silicon layer 10c, second insulatingfilm 11 and first polysilicon layer 12. The second single crystalsilicon layer 14 is defined as intrinsic base region. An n-type thirdsingle crystal silicon layer (i.e., fourth semiconductor layer) 15 isprovided to cover the second single crystal silicon layer 14 on a sideof the layer 14, which is opposite to the other side thereof in contactwith the first single crystal silicon layer 10c and the firstpolysilicon layer 12. An n-type second polysilicon layer 16 is providedover the first polysilicon layer 12 with a third insulating film 13 ofsilicon dioxide interposed therebetween. The second polysilicon layer 16is located over one end of the first polysilicon layer 12 and connectedto the third single crystal silicon layer 15. The third single crystalsilicon layer 15 and the second polysilicon layer 16 together constitutean emitter region. n n-type third polysilicon layer 17 is furtherprovided on the first insulating film 10b to extend along the firstinsulating film 10b. One end of the third polysilicon layer 17 isconnected to the side of the third single crystal silicon layer 15. Thethird polysilicon layer 17 is defined as extension of the emitterregion.

[0035] A fourth insulating film 18 of silicon dioxide is furtherprovided to cover the first and third single crystal silicon layers 10cand 15 and the first, second and third polysilicon layers 12, 16 and 17.And emitter, base and collector electrodes 19A, 19B and 19C are providedon the fourth insulating film 18 so as to be connected to the thirdpolysilicon layer (emitter extension region) 17, the first polysiliconlayer (base extension region) 12 and first single crystal silicon layer(collector region) 10c, respectively.

[0036] Hereinafter, a method for fabricating the bipolar transistor willbe described with reference to FIGS. 2(a) through 2(d).

[0037] First, as shown in FIG. 2(a), the SOI substrate 10 is prepared.In the SOI substrate, the n-type first single crystal silicon layer(first semiconductor layer) 10c has been deposited over the siliconsubstrate 10a with the first insulating film 10b of silicon dioxideinterposed therebetween. The first single crystal silicon layer 10c,which will constitute a collector region, may be doped with As and havea resistivity of 0.3 Ω • cm. Alternatively, the n-type first singlecrystal silicon layer 10c may be newly deposited over the siliconsubstrate 10a with the first insulating film 10b interposed therebetweenin the fabrication process of the bipolar transistor.

[0038] Next, the second insulating film 11 of silicon dioxide isdeposited by a chemical vapor deposition (CVD) process to a thickness of100 nm on the first single crystal silicon layer 10c of the SOIsubstrate 10. Then, the p-type first polysilicon layer (secondsemiconductor layer) 12, which is doped with B at a carrier density of1×10²⁰/cm³, is deposited by a CVD process again to a thickness of 300 nmon the second insulating film 11. The first polysilicon layer 12 will bean extension region for the intrinsic base region that will be formedlater.

[0039] Subsequently, the third insulating film 13 of silicon dioxide isdeposited by a CVD process, for example, to a thickness of 300 nm on thefirst polysilicon layer 12. Thereafter, a first resist pattern (notshown) is defined on the third insulating film 13. And the thirdinsulating film 13, first polysilicon layer 12, second insulating film11 and first single crystal silicon layer 10c are etched and patternedanisotropically using the first resist pattern as a mask.

[0040] Then, as shown in FIG. 2(b), the p-type second single crystalsilicon layer (third semiconductor layer) 14 is selectively grownepitaxially by a CVD process to a thickness of 60 nm on the side facesof the first single crystal silicon layer 10c, second insulating film 11and first polysilicon layer 12. The second single crystal silicon layer14 will be the intrinsic base region.

[0041] Next, an epitaxy process is performed under such conditions asgrowing epitaxial and polysilicon layers at the same time. In thismanner, the n-type third single crystal silicon layer (fourthsemiconductor layer) 15 is grown on the side of the second singlecrystal silicon layer 14. Also, the n-type second polysilicon layer 16is grown on the third insulating film 13 so as to be connected to thethird single crystal silicon layer 15. Furthermore, the n-type thirdpolysilicon layer (fifth semiconductor layer) 17 is grown on the firstinsulating film 10b so as to be also connected to the third singlecrystal silicon layer 15. The third single crystal silicon layer 15 willbe the emitter region, while the third polysilicon layer 17 will be theemitter extension region.

[0042] Then, as shown in FIG. 2(c), the second polysilicon layer 16 andthird insulating film 13 are etched and patterned anisotropically usinga second resist pattern (not shown) as a mask. Thereafter, the firstpolysilicon layer 12 and second insulating film 11 are etched andpatterned anisotropically using a third resist pattern (not shown) as amask. Subsequently, the first single crystal silicon layer 10c and thirdpolysilicon layer 17 are etched and patterned anisotropically using afourth resist pattern (not shown) as a mask.

[0043] Thereafter, as shown in FIG. 2(d), the fourth insulating film 18of silicon dioxide is deposited by a CVD process over the entire surfaceof the substrate. Then, electrode openings are provided in the fourthinsulating film 18 by etching anisotropically the fourth insulating film18 using a fifth resist pattern (not shown) as a mask. Next, an aluminumfilm, for example, is deposited over the entire surface of the fourthinsulating film 18 and then patterned, thereby forming the emitter, baseand collector electrodes 19A, 19B and 19C. In this manner, the inventivenpn junction bipolar transistor is obtained.

[0044] According to the present invention, the height of the secondsingle crystal silicon layer 14 to be the base region is defined as thetotal thickness of the first single crystal silicon layer 10c, secondinsulating film 11 and first polysilicon layer 12. And the thicknessesof the first single crystal silicon layer 10c, second insulating film 11and first polysilicon layer 12 are each controllable precisely. Also,the area of a junction region between the third single crystal siliconlayer 15 to be the emitter region and the second single crystal siliconlayer 14 to be the base region is defined by the height of the secondsingle crystal silicon layer 14.

[0045] Thus, the area of the emitter-base junction region iscontrollable precisely, so is the emitter-base parasitic capacitance. Asa result, the electrical characteristics of the bipolar transistor canbe stabilized.

[0046] In addition, the thicknesses of the first single crystal siliconlayer 10c, second insulating film 11 and first polysilicon layer 12 canall be reduced by adjusting the deposition conditions. Accordingly, theoperating speed of the bipolar transistor can be increased by reducingthe emitter-base parasitic capacitance through the reduction in totalthickness of the first single crystal silicon layer 10c, secondinsulating film 11 and first polysilicon layer 12.

[0047] Moreover, the first single crystal silicon layer 10c is patternedafter the first polysilicon layer 12 has been patterned. Accordingly,the area of the first polysilicon layer 12 can be smaller than that ofthe first single crystal silicon layer 10c. That is to say, thecollector electrode 19C can be directly connected to the first singlecrystal silicon layer 10c, thus cutting down the number of processsteps.

[0048] In the foregoing embodiment, the intrinsic base region is made ofthe p-type second single crystal silicon layer 14. Alternatively, thebase region may be made of p-type silicon germanium. The band gap of thesilicon germanium layer is smaller than that of the silicon layer. Thus,discontinuity is caused between the valence band of the first and thirdsingle crystal silicon layers 10c and 15 functioning as the collectorand emitter regions and that of the intrinsic base region in such anembodiment. As a result, the number of holes injected from the baseregion into the emitter region decreases and the frequencycharacteristics of the bipolar transistor improve.

[0049] Also, in the foregoing embodiment, the first and third singlecrystal silicon layers 10c and 15 are defined as collector and emitterregions, respectively. Alternatively, the first and third single crystalsilicon layers 10c and 15 may be defined as emitter and collectorregions, respectively. In such a case, the third polysilicon layer 17will be a collector extension region.

[0050] Furthermore, the present invention has been described as beingapplied to an npn junction bipolar transistor and a method forfabricating the same. Alternatively, the present invention is naturallyapplicable to a pnp junction bipolar transistor.

What is claimed is:
 1. A method for fabricating a bipolar transistor,comprising the steps of: forming a first semiconductor layer of a firstconductivity type, an insulating film and a second semiconductor layerof a second conductivity type in this order over a semiconductorsubstrate; forming a third semiconductor layer of the secondconductivity type on respective side faces of the first and secondsemiconductor layers and the insulating film; forming a fourthsemiconductor layer of the first conductivity type on a side of thethird semiconductor layer, the side being opposite to the other side ofthe third semiconductor layer that is in contact with the first andsecond semiconductor layers; forming a fifth semiconductor layer of thefirst conductivity type over the semiconductor substrate such that thefifth semiconductor layer is in contact with the fourth semiconductorlayer; and defining the third semiconductor layer as a base region, thefirst semiconductor layer as one of collector and emitter regions, thefourth semiconductor layer as the other of the collector and sitterregions, the second semiconductor layer as an extension of the thirdsemiconductor layer and the fifth semiconductor layer as an extension ofthe fourth semiconductor layer, respectively.
 2. The method of claim 1,wherein the area of the second semiconductor layer is smaller than thatof the first semiconductor layer.
 3. The method of claim 1 wherein thefirst and fourth semiconductor layers are silicon layers, and whereinthe third semiconductor layer is a silicon germanium layer.
 4. Themethod of claim 1, wherein the steps of forming the fourth and fifthsemiconductor layers are performed as a single process step.